1. Technical Field
The present invention relates to a clock synchronization circuit that is able to compensate for a skew between an external clock signal and an internal clock signal and, in particular, to a clock synchronization circuit that can precisely synchronize clock signals regardless of noise generated due to shift in delay lines by using two delay lines and a phase mixer.
2. Description of the Background Art
In general, a clock synchronization circuit such as a delay locked loop (DLL), or a phase locked loop (PLL) is used as a clock generating device for compensating for a skew between an external clock signal and an internal clock signal.
Referring to FIG. 1, a conventional clock synchronization circuit includes: a variable delay line 1 for delaying an external clock signal EXCLK for a predetermined time and for generating an internal clock signal INCLK; a delay monitor 2 for monitoring a delay time of the internal clock signal INCLK from the variable delay line 1; a phase detector 3 for comparing a phase difference between the external clock signal EXCLK and the internal clock signal INCLK, and outputting shift signals SHL and SHR for adjusting the phase difference; and a shift register 4 for controlling the delay time of the variable delay line 1 according to the shift signals SHL and SHR from the phase detector 3.
The variable delay line 1 delays the external clock signal EXCLK for a predetermined time, and outputs the internal clock signal INCLK. Here, the internal clock signal INCLK is inputted to the phase detector 3 through the delay monitor 2, so that the phase detector 3 judges whether the internal clock signal INCLK has a faster or slower phase than the external clock signal EXCLK.
The phase detector 3 controls the shift register 4 according to the shift signals SHL and SHR, so that the external clock signal EXCLK and the internal clock signal INCLK have the same phase.
The shift register 4 outputs control signals SL1-SLN according to the shift signals SHL and SHR. The variable delay line 1 controls a delay time of the external clock signal EXCLK so that a phase of the external clock signal EXCLK can be synchronized with a phase of the internal clock signal INCLK.
As shown in FIG. 2, the variable delay line 1 includes: NAND gates ND1-NDN for selectively outputting the external clock signal EXCLK according to the output signals SL1-SLN from the shift register 4; unit delay cells DEL1-DELN connected in series for delaying the external clock signal EXCLK selectively outputted by the NAND gates ND1-NDN; and a NAND gate NDA for NANDing a power voltage VCC and the output signal from the last unit delay cell DELN and for outputting the internal clock signal INCLK.
Here, the unit delay cell DELi includes: a NAND gate ND1i for NANDing the output signal from the previous unit delay cell DEL(ixe2x88x921) and the output signal from the NAND gate NDi; a NAND gate ND2i for NANDing the power voltage VCC and the output signal from the NAND gate ND1i. 
The operation of the conventional clock synchronization circuit will now be explained.
When it is presumed that the second signal of the output signals SL1-SLN from the shift register 4 has a high level and the other signals SL1-SL(Nxe2x88x922) and SLN have a low level in an early stage, the external clock signal EXCLK is delayed through a delay path from the second delay cell DEL(Nxe2x88x921) to the last delay cell DELN, and outputted as the internal clock signal INCLK.
Here, the phase detector 3 compares the phase of the external clock signal EXCLK with the phase of the internal clock signal INCLK. When the phase of the external clock signal EXCLK is faster than that of the internal clock signal INCLK, the phase detector 3 outputs the control signal SHL to shift left the shift register 4.
Because the second signal SL(Nxe2x88x921) of the output signals SL1-SLN from the shift register 4 has a high level and the other signals SL1-SL(Nxe2x88x922) and SLN have a low level in an early stage, the third signal SL(Nxe2x88x922) of the output signals SL1-SLN from the shift register 4 has a high level and the other signals SL1-SL(Nxe2x88x923), SL(Nxe2x88x921) and SLN have a low level according to the control signal SHL from the phase detector 3. Accordingly, the external clock signal EXCLK is delayed through a delay path from the third delay cell DEL(Nxe2x88x922) to the last delay cell DELN, and outputted as the internal clock signal INCLK.
Conversely, when the phase detector 3 compares the phase of the external clock signal EXCLK with the phase of the internal clock signal INCLK, if the phase of the external clock signal EXCLK is slower than that of the internal clock signal INCLK, the phase detector 3 outputs the control signal SHR to shift right the shift register 4. Because the second signal SL(Nxe2x88x921) of the output signals SL1-SLN from the shift register 4 has a high level and the other signals SL1-SL(Nxe2x88x922) and SLN have a low level in an early stage, the first signal SLN of the output signals SL1-SLN from the shift register 4 has a high level and the other signals SL1-SL(Nxe2x88x921) have a low level according to the control signal SHR from the phase detector 3. Therefore, the external clock signal EXCLK is delayed through a delay path of the last delay cell DELN, and outputted as the internal clock signal INCLK.
In the conventional clock synchronization circuit for the semiconductor memory device, the variable delay line 1 includes the unit delay cells DEL1-DELN connected in series and each respectively having two serially-connected NAND gates.
Accordingly, a number of the unit delay cells DELi increases or decreases to adjust a delay time. Here, the shift right or left is performed in unit delay cell units according to the output signals SL1-SLN from the shift register 4 to increase or decrease the number of the unit delay cells DELi.
However, the phase is suddenly changed for a time period as long as the delay time of the unit delay cell DELi. As shown in FIG. 3, when the shift is generated in time point xe2x80x98A,xe2x80x99 the internal clock signal INCLK has a jitter. In addition, a pulse width of the clock varies, and thus a clock period is changed.
A clock synchronization circuit may include at least two variable delay lines for respectively delaying an external clock signal for a different delay time and at least two shift registers for respectively controlling the delay time of the variable delay lines. The circuit may also include a phase mixer for mixing phases of the clock signals delayed by the variable delay lines, and outputting an internal clock signal having a phase between the phases of the delayed clock signals; a phase detecting unit for comparing the phase of the external clock signal with the phase of the internal clock signal, and outputting the result; and a control unit for outputting a first control signal for determining the phase of the internal clock signal from the phase mixer, and a second control signal for controlling a shift operation of at least one shift register among the shift registers according to the comparison result of the phase detecting unit.
A second clock synchronization circuit may include a normal internal clock signal generator for generating a normal internal clock signal to be synchronized with an external clock signal and an inverted internal clock signal generator for outputting an inverted internal clock signal to be synchronized with a phase-shifted clock signal of the external clock signal. In such an arrangement, the normal internal clock signal is transmitted to circuits operated on a rising edge of the internal clock signal and the inverted internal clock signal is transmitted to circuits operated on a falling edge of the clock signal.